Conventional serializer and deserializer circuits (SERDES) are often used to transmit high speed parallel data across a lossy channel. For a set of high speed parallel data, the timing or synchronization is difficult to achieve when the set of data is sent out through different paths.
For this reason, the parallel data can be first converted into serial data in a transmitter. Then the transmitter will send out the serial data with a certain amplitude to a remote receiver across a lossy channel. The receiver then amplifies the attenuated input signal. The amplified signal is sampled by a clean clock to remove noise. The phase of the received signal is aligned to a well defined clock phase. The received serial signal is then converted back to a parallel digital signal. The channel is usually built by transmission lines in a printed circuit board. With higher data rates and longer channels, the loss is large.
Conventional approaches often implement a pre-emphasis circuit in the transmitter and a linear equalizer and decision feedback equalizer (DFE) in the receiver. The pre-emphasis and equalization circuits are built in the SERDES to remove inter-symbol interference (ISI).
The equalization circuits implemented in receivers tend to use a lot of power. If there are no real data received in the receivers, the equalization circuit can be powered down in order to save power, which needs a circuit to determine the effectiveness of the received signal. In general, a circuit with this function is called loss of signal detector (LOS). Conventional approaches implement a loss of signal detector at a receiver to continuously monitor the channel data and the link status. If the output of the loss of signal detector is high (or effective), an indication is sent that the channel data is lost or the received data is too small to power up the other signal processing circuit in the receiver.
A loss of signal detector includes a linear amplifier to amplify the received data, a rectifier to convert the amplified AC signal to DC voltage, a comparator to compare the rectified DC voltage with a reference voltage. The output of the comparator is sent to the digital control core of the SERDES. For data communication, the data rate processed by a SERDES is increased from a few Gbps up to 30 Gbps. Data rates tend to continuously increase as designs evolve.
To enable the loss of signal circuit to differentiate significantly attenuated data from noise is challenging. With the progress of CMOS technology, supply voltages tend to scale down, but the data rates tend to increase. The attenuation across a circuit board proportionally decreases the data rate. The overall effect is that with a smaller feature size, a lower supply voltage, a faster operating speed and a larger attenuation, the signal amplitude at the far end of a remote receiver decreases. The signal to noise ratio (SNR) also decreases. Therefore, the sensitivity of a LOS circuit has to increase. Since the received data could be in any frequency range (from 100 Mbps up to 30 Gbps), LOS circuits need to maintain an ultra wide bandwidth.
U.S. Pat. No. 6,377,082, entitled “Loss-of-Signal Detector for Clock Data Recovery Circuit”, discloses using clock and data recovery (CDR) circuit to detect the loss of signal. One drawback with such an approach is the reliance on the function of the CDR decision circuit. The pre-requirement for the functionality of a CDR decision circuit is that the input signal amplitude has to be large enough. Such an approach is power hungry since most of the blocks in receiver need to be powered on.
U.S. Pat. No. 4,868,470, entitled “Apparatus and Method for Detecting a True Average of N Signal Samples”, discloses an average detector in bipolar technology, which uses an input capacitor C, an output capacitor nC, and a number of diodes. Such an architecture can not be applied in low voltage CMOS process.
U.S. Pat. No. 7,102,392, entitled “Signal Detector for High-Speed SerDes”, discloses an improved signal detector by using two peaking amplifiers to amplify simultaneously the differential received signals and differential reference voltages. The major drawback is that such an approach consumes large amounts of power due to the power consumption of the peaking amplifier. Another issue is that the gain for the reference voltage from a peaking amplifier is a DC gain. The gain for input signal is a large-signal AC gain. The gain from these two peaking amplifiers can not be accurately matched.
It would be desirable to implement an ultra-wideband loss of signal detector that may be used at a receiver for high speed SERDES application.